OSS + ELC EU 2026

Clocks are easy to ignore until your first Zephyr BSP port — when UART, SPI, or DMA suddenly depend on device tree properties you have never touched.
This beginner-friendly talk explains how clocks work in Zephyr today: clocks as phandle-arrays (like pwms and gpios), the meaning of #clock-cells, and how DT macros connect DTS to driver code. We separate three everyday questions: enabling a clock, selecting its source, and reading its rate — mapped to clock_control_on(), clock_control_configure(), and get_rate().
We then cover practical porting decisions any SoC author faces: what to describe in device tree at boot, what to leave to runtime (for example power management), and common mistakes — wrong cells, gates versus muxes and over-modelling hardware in DT.
Finally, we look at where Zephyr is heading: RFCs for a Clock Management Subsystem propose richer clock trees and predefined clock states, closer to how silicon is wired. You will leave with a reusable mental model for today’s APIs and a map of tomorrow’s direction.
Audience: developers new to Zephyr, BSP porters, and device tree authors. No prior clock-driver experience required.