OSS + ELC EU 2026

Embedded developers optimizing Zephyr applications often rely on software timers and GPIO toggles—intrusive techniques that alter the behavior they try to measure. Modern SoCs instead provide rich hardware performance counters across the system: CPU PMUs, interconnect/NoC monitors, and memory subsystem telemetry that capture cycles, cache behavior, bandwidth, and contention with near-zero overhead. Until now, Zephyr lacked a unified way to access these metrics.

This talk introduces Zephyr’s new portable **pmu.h** API, a cross-architecture abstraction for hardware performance monitoring. We present the first backend: an ARMv8-A PMUv3 driver that probes counters at runtime, self-calibrates CPU frequency, and maintains per-CPU state using IRQ-locked sequences for SMP safety.

Using real hardware benchmarks, we show how to measure context-switch cost, IRQ latency, cache behavior, branch prediction, and memory bandwidth. Attendees will learn how to add low-overhead profiling to their applications today and how the API will extend to RISC-V HPM, Cortex-M DWT, and SoC-level monitors without changing application code.

Pull request: https://github.com/zephyrproject-rtos/zephyr/pull/107016