OSS + ELC EU 2026

Multi-core ARM Cortex-M SoCs are becoming increasingly common in today's market. Yet Zephyr RTOS only supports Asymmetric Multiprocessing (AMP) for these devices. The problem with AMP is that it limits true resource sharing, and leaves hardware parallelism underutilized. Symmetric Multiprocessing (SMP) addresses these issues by running a single Zephyr RTOS image with a unified scheduler across all cores. Zephyr RTOS currently lacks support for Symmetric Multiprocessing on ARM Cortex-M based SoCs and hence limits multi-core Cortex-M devices to AMP configurations. This talk presents a Proof-of-Concept implementation of SMP on Dual Core Cortex-M7 cores using the Infineon Traveo T2G (CYT4DN) SoC which runs a single Zephyr image with true parallel execution across cores.

The key framework challenges are: lack of a secondary boot up path for the secondary cores and the complications of unified timekeeping with per-core SysTick timers.

The talk details what has been achieved, the limitations that remain in timeout-driven context switching and scheduling, and outlines a path toward upstream-ready Cortex-M SMP support in Zephyr.